1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more specifically, to an electrically rewritable and collectively erasable non-volatile semiconductor memory device (FLASH EEPROM).
2. Description of the Background Art
FIG. 8 is a block diagram of a conventional FLASH EEPROM which is one of non-volatile semiconductor memory devices.
A non-volatile semiconductor memory device means a memory device in which the stored content is not erased even if power supply is turned of. The non-volatile semiconductor memory devices comprise electrically erasable EPROMs and EEPROMs (electrically erasable PROM). In the EPROMs, an ultraviolet ray, a x-ray or the like is used to erase data. In the EEPROMs, erasing and rewriting of data are carried out electrically. The EEPROMs comprise normal type EEPROMs and flash type EEPROMs.
In the normal type EEPROM, a selecting transistor is provided in each memory cell and it is adapted such that when the data is read, the data stored in the memory cell does not appear on the corresponding bit line until the selecting transistor is turned on.
Referring to the figure, the non-volatile semiconductor memory device comprises an address buffer 7 to which addresses of memory cells for storage are inputted; a column decoder 8 to which column addresses are inputted; a row decoder 9 to which row addresses are inputted; a high voltage switch 10 for switching potential on word lines; an I/O buffer 11 for inputting/outputting data; a sense amplifier/write driver 12 for amplifying read data or for holding write data; a Y gate 13 for selecting a prescribed bit line; a memory cell array 14 having memory cells arranged in a matrix; a high voltage control circuit 19 for controlling the high voltage to be applied to the memory cell array 14; a control signal buffer 20 to which control signals are inputted; a control circuit 21 for controlling various operations; and an array source switch 22 for switching potential of the source of the memory cell array. A structure of a memory cell is shown in the memory cell array 14 as a representative. A memory cell 18 is arranged at an intersection of a bit line 15 and a word line 16. The drain of the memory cell 18 is connected to the bit line 15. The source of the memory cell 18 is connected to a source line 17, and the other end of the source line is connected to the array source switch 22. The word line 16 is connected to the floating gate of the memory cell 18.
The operation of the non-volatile semiconductor memory device structured as above will be described.
The operation of the non-volatile semiconductor memory device includes writing, erasing and reading operations.
Before writing, information stored in the memory cells of all addresses must be erased.
First, writing operation will be described.
The address data of an address to which writing should be done is inputted through the address buffer 7, and a control signal for enabling writing is inputted through the control signal buffer 20. Then a high voltage V.sub.pp is applied to the high voltage control circuit 19. The inputted address data is decoded by the row decoder 9 and correspondingly a word line is selected. The inputted high voltage V.sub.pp is controlled by the high voltage control circuit 19 to be applied to the high voltage switch 10.
The high voltage switch 10 of the selected word line sets the selected word line at a high voltage, and the high voltage switches of other non-selected word lines output 0 V. Meanwhile, the data inputted through the I/O buffer 11 is latched by the write driver 12. The write driver 12 applies a high voltage to the bit line including the bits to which the information "0" is to be written, and applies the potential of 0 V to the bit lines including bits to which the information "1" is to be written, through the Y gate 13 selected by the column decoder 8. At this time, the potential of the source line is maintained at 0 V by the array source switch 22 switched based on the signal outputted from the control circuit 21.
The schematic structure of the memory cell 18 will be described with reference to FIG. 10.
Two impurity regions are formed spaced apart by a prescribed distance on a main surface of a semiconductor substrate 5, one of which serves as the drain 3, and the other one serves as the source 4. An insulating film 6 is formed on that region of the semiconductor substrate 5 which is sandwiched by the drain 3 and the source 4, and floating gate 2 is formed thereon. A control electrode 1 is formed above the floating gate 2, with an insulating material 6a located therebetween. In this structure, in a memory cell to which the information "0" is written, the high voltage V.sub.pp is applied to the control gate 1, that is, the word line 16, a write voltage V.sub.BR is applied to the drain 3, that is, the bit line 15, and the potential 0 V is applied to the source 4, that is, the source line 14. Therefore, in this state, an avalanche breakdown occurs near the drain 3 of the memory cell, generating hot electrons. The hot electrons accelerated by the high voltage on the control gate 1 go over the barrier of the oxide film 6 to enter the floating gate 2, where the hot electrons are stored. By the writing operation, the threshold voltage of the memory transistor having the information "0" written therein becomes higher than before the writing operation. Namely, even if the supply voltage V.sub.CC (5 V) is applied to the control gate 1, the transistor is not turned ON.
Meanwhile, in the memory cell having the information "1" written therein, the potential of the bit line 15 is 0 V, and hot electrons are not generated. Therefore, the state is the same as that before writing. Namely, this state is the erased state with low threshold voltage.
The erasing operation will be described.
The erasing operation includes two operations, that is, writing of the information "0" to all addresses, and collective erasing of the memory cells of all addresses.
The reason why writing of the information "0" to all addresses is necessary will be described with reference to FIGS. 12A and 12B.
FIG. 12A shows a change of the threshold voltage of a memory transistor when writing and erasing are carried out in a conventional device, and FIG. 12B shows the change of the threshold voltage of the memory transistor when writing of the information "0" of all addresses is omitted in the erasing operation on a conventional device.
In the collective erasing operation, the potential of 0 V is applied on the control gate 1 of the memory cell, the drain 3 is kept at a floating state, and a high voltage is applied to the source 4. In this voltage condition, a high electric field is generated between the source 4 and the floating gate 2. By the high electric field, the electrons included in the control gate 2 are removed to the source 4, and as a result, the threshold voltage of the memory transistor is lowered. However, if this erasing operation is done when the original threshold voltage is low (when the information "1" has been written), the threshold voltage of the memory cell which has the information "1" written therein becomes a negative value, as shown in FIG. 12B, causing troubles in reading information.
FIG. 11 shows the change of the threshold voltage describing such trouble.
Referring to the Figure, the abscissa represents the erasing time, and the ordinate represents the threshold voltage of the memory transistor. It shows the change of the threshold voltage of a memory transistor M.sub.0 in which information "0" is written, and the change of the threshold voltage of a memory transistor M.sub.1 in which information "1" is written.
As the erasing time passes, the threshold voltages of both memory transistors decrease gradually. At the time T when the threshold voltage of the memory transistor M.sub.0 reaches the threshold voltage V of the memory transistor M.sub.1 before erasing thus completing erasing, the threshold voltage of the memory transistor M.sub.1 has come to be a negative value.
FIG. 9 is a schematic diagram showing structures of some memory cells on the matrix, arranged in the memory cell 14 of FIG. 8.
Referring to the figure, memory cells M.sub.11 to M.sub.44 are arranged at intersections of word lines W.sub.1 to W.sub.4 and bit lines B.sub.1 to B.sub.4. The sources of the memory cells are connected to the source lines S.sub.1 to S.sub.4, respectively. The above mentioned troubles in reading will be described with reference to the structure of FIG. 9.
In reading operation of this device, the supply voltage V.sub.CC is applied to the word line, that is, the control gate 1 of the selected memory cell, and the potential 0 V is applied to the word lines of other non-selected memory cells. Whether or not the memory transistor of the selected memory cell is turned ON or not, that is, whether current flows to the bit line or not is detected. For example, referring to FIG. 9, let us assume that the memory cell M.sub.22 is the selected memory cell, and the memory cell M.sub.42 has its threshold value lower than the normal state by the collective erasing operation described above.
In this case, the word line W.sub.2 is selected and the supply voltage V.sub.CC is applied. However, the word line W.sub.4 is not selected, so that the potential thereof is kept at 0 V. If the information "0" has been written in the memory cell M.sub.22, the memory transistor is not turned on even when the word line W.sub.2 is selected, that is, no current flows through the bit line B.sub.2. However, if the threshold voltage of the memory cell M.sub.42 is a negative value, the memory transistor is turned ON even if the word line W.sub.4 is not selected. As a result, a current flows through the bit line B.sub.2 connected to the memory transistor M.sub.42, resulting in misdetermination that the information "1" is written in the memory transistor M.sub.22. In this manner, if any of the memory cells connected to the bit lines has a negative threshold voltage value, current flows to the bit line even if the memory cell is not selected. Accordingly, the correct information of the selected memory cell can not be read.
Such a problem is inherent to the flash type EEPROM and does not arise in the normal type EEPROM as described above. The reason for this is that each memory cell has a selecting transistor in the normal type EEPROM. Therefore, even if the threshold voltage of one memory cell attains negative, current does not flow to the bit line unless the selecting transistor of that memory cell is turned ON, and therefore, reading from other memory cells are not affected.
In addition, such a problem does not arise in the EPROM. Since erasing of data in the EPROM is carried out by irradiation of a ultraviolet ray or the like, excessive removal of electrons as described above does not occur.
In order to solve the above described problem, writing of the information "0" is carried out on memory cells of all addresses before the collective erasing operation of the memory cells, as shown in FIG. 12A. Namely, the threshold voltages of all memory cells are once set to high threshold value and thereafter collective erasing is done. Consequently, the erased memory cells have the positive threshold voltages lower than the supply potential V.sub.CC, resulting in high reliability. The operation of writing the information "0" to the memory cells of all addresses is done in the same manner as usual, namely, the information "0" is successfully written to all addresses.
The collective erasing operation will be described.
The collective erasing is started by applying a high voltage to the high voltage control circuit 19 and by inputting a control signal enabling the collective erasing to the control signal buffer 20. The inputted high voltage is controlled by the high voltage control circuit 19 to be applied to the array source switch 22. The array source switch 22 receives the control signal from the control circuit 21, that is, the signal to start erasing, and outputs a high voltage to the source line 17. At this time, all of the word lines 16 in the memory cell array 14 have the potential 0 V, and all of the bit lines 15 are kept in the floating state. Referring to FIG. 9, all the memory cells have their sources 4 set at a high voltage, the control gates 1 set at 0 V, and drains 3 kept in the floating state. Consequently, a high electric field is generated between the floating gate 1 and the source 4 of the memory transistor, the electrons in the floating gate 2 move to the source 4 by the tunnel phenomenon, and therefore the threshold voltage of the memory transistor becomes lower than before the erasing operation.
The reading operation will be described.
In the reading operation, the address data designating the address of the memory cell holding the information to be read is written to the address buffer 7. One word line of the memory cell array 14 is selected by the same operation as the writing operation, and a prescribed bit line 15 is selected by the Y gate 13 based on the information decoded by the column decoder 8. Only the selected word line is set to the supply voltage V.sub.CC and the potential of other word lines is 0 V. The sense amplifier 12 connected to the selected bit line 15 detects whether the memory transistor connected to the selected word line is in ON state (low threshold voltage) or in OFF state (high threshold voltage). If it is in ON state, the information "1" is externally outputted, and if it is in OFF state, the information "0" is externally outputted, through the I/O buffer 11.
In the above described conventional non-volatile semiconductor memory device, writing of the information "0" must be carried out on the memory cells of all addresses when erasing operation is to be done. FIG. 13 is a flow chart showing the contents of the erasing operation, and FIG. 14 shows changes of potentials on the word line, bit line and source line in respective ones of the writing to the reading operations.
As shown in FIG. 13, when the erasing operation is started, whether or not the information stored in the memory cells of all addresses is "0" is determined in the step S11. If the information is not 0 in all the memory cells, the address to be written is incremented by 1 in the step S13, and the information "0" is written in the step S15. Then whether or not the address to be written is the last address is determined in the step S17. If it is not the last address, the program returns to the step S13 to repeat the writing of the information "0", and this operation is continued until the address reaches the last address. If it reached the last address and the information "0" is written in the memory cells of all addresses, erasing operation to set the information in all the memory cells to "1" is done in the step S19. Whether or not all the memory cells have the information "1" is determined in the step S21. This operation is repeated until all the memory cells have the information "1", that is, all the memory cells are set in the erased state. The erasing operation is completed when all the memory cells have the information
Referring to FIG. 14, writing operation is done at first to the memory cell of the selected address under the potential condition as shown in the figure. Then, when the erasing operation is started, the information "0" is written to the memory cells of all the addresses in succession by the same manner as the normal writing operation. Namely, the state of the potentials on the word line, bit line and source line are the same when the information "0" is written in the normal writing operation and in the writing operation of the erasing operation. In the collective erasing operation, only the source line is set at the high voltage V.sub.PP. The potential of the word line and the bit line is 0 V. In the reading operation, the word line is at the supply voltage V.sub.CC, the bit line is at the read potential V.sub.BR and the source line is at 0V.
Now, as the capacity of the memory device is increased, the time required for writing the information "0" to the memory cells of all addresses in the above described erasing operation becomes very long. For example, in a FLASH EEPROM of 1 megabyte, the time required for writing "0" to all addresses is 1 to 2 seconds. The long time required for the writing of all addresses leads to long time for the erasing operation, which is inconvenient for the user.
Further, writing of information "0" to the memory cells of all addresses is carried out by using hot electrons as described above, so that the power consumption is as large as about 1 mA per 1 memory cell.